This invention relates to a variable delay circuit, which generates a delay amount. In particular, this invention relates to a variable delay circuit, which has a plurality of variable delay elements and generates a desired delay amount. Moreover, this invention relates to a Japanese patent application shown below. For the designated state that permits the incorporation of the literature by reference, the contents mentioned in the application shown below are incorporated into the present application to be a part of the contents of the present application.
Japanese patent application H11-193774, filed on Jul. 7th, 1999.
FIG. 1 shows a block diagram of the conventional variable delay circuit 100. The variable delay circuit 100 comprises a micro-variable delay unit 12 and a variable delay unit 14. The micro-variable delay unit 12 has micro-variable delay elements (12a-12n). The variable delay unit 14 has a delay unit (14a-14n). The micro-variable delay elements 12 generate the delay amount, which is smaller than the delay amount generated by the delay unit (14a-14n). Each of the delay units (14a-14n) has a different number of gate circuits 11 and generates a delay amount according to the number of gate circuits 11.
According to the desired delay amount, a delay data, which designates any one of a combination of the micro-variable delay elements (12a-12n) and the delay units (14a-14n), is provided. An input signal is input and is delayed by the delay element selected by the delay data, and a delay signal is output.
FIG. 2(a) is a circuit diagram that shows a drive-impedance-control-type micro-variable delay element 12. In a case where a control signal has a truth value of xe2x80x9c0xe2x80x9d, a drive impedance is set to low. In a case where a control signal has a truth value of xe2x80x9c1xe2x80x9d, a drive impedance is set to high. Therefore, in a case where the control signal has a truth-value of xe2x80x9c1xe2x80x9d, the input signal has a delayed output which is a few more than the case of when the truth value is xe2x80x9c0xe2x80x9d.
FIG. 2(b) is a circuit diagram of a load-capacity-variable-type of micro-variable delay element 12 In a case where a control signal has a truth value of xe2x80x9c0xe2x80x9d, a load capacity is not set, and in a case where a control signal has a truth value of xe2x80x9c1xe2x80x9d, the load capacity is set. Therefore, in a case where the control signal has a truth value of xe2x80x9c1xe2x80x9d, the input signal has a delayed output which is a few more than the case of when the truth value is xe2x80x9c0xe2x80x9d. The variable delay circuit 100 shown in FIG. 1 has a micro-variable delay element 12 shown in FIG. 2(a) and FIG. 2(b) and generates a delay amount in a degree from 10 ps to 100 ps for one micro-variable delay element 12.
FIG. 3 shows a graph for showing the relationship between the delay data, which designates the combination of the delay elements according to the design for generating the desired delay amount, and the delay amount, which is actually generated by the combination of the delay elements set by the delay data. A line xe2x80x9caxe2x80x9d shows a straight line, which shows an ideal delay characteristic. In comparison to this, the line xe2x80x9cbxe2x80x9d generates a delay amount larger than the ideal delay amount. The line xe2x80x9ccxe2x80x9d generates the delay amount smaller than the ideal delay amount.
Furthermore, the line xe2x80x9cbxe2x80x9d and the line xe2x80x9ccxe2x80x9d have a discontinuous part. This is because there are a plurality of different types of the variable delay elements existing in the variable delay circuit 100, and also because the unevenness of the element characteristics and the influence of the change of the ambient temperature do not necessarily match for each type of the variable delay elements.
There is a case that an error is caused on the delay amount, which is generated by the variable delay circuit 100 between the delay amount actually generated by the delay elements and the delay amount according to the design, by such as the unevenness of the element characteristics of the delay elements, a fluctuation of the self-generated heat quantity of the delay element, a fluctuation of the ambient temperature, and a fluctuation of a power supply voltage.
Therefore, it is an object of the present invention to provide a variable delay circuit that can overcome the above issues. This object is achieved by combinations of characteristics described in the independent claims in the scope of the claim of the invention. The dependent claims define further advantageous embodiments of the present invention.
To solve the above object, the first embodiment of the present invention is a variable delay circuit for generating a desired delay amount comprises: a delay compensation unit, which has a plurality of referential delay units that include different numbers of first variable delay elements, the delay amount of which varies based on a control signal, the delay compensation unit generates each of a plurality of the control signals, which are provided to the first variable delay elements included in each of the plurality of referential delay elements, according to a number of the first variable delay elements included in each of the plurality of referential delay units; and a delay unit which generates the desired delay amount by controlling a plurality of second variable delay elements, which have a same characteristic with the first variable delay elements, by the plurality of control signals.
The referential delay unit may include: a first referential delay unit which has M numbers (M is a natural number) of the variable delay elements; a second referential delay unit that has N numbers (N is a natural number) of the first variable delay elements, the numbers of which are different to the numbers of the first variable delay elements included in the first referential delay unit; the delay compensation unit may have: a first delay compensation unit that generates the control signal provided to the first variable delay elements included in the first referential delay unit; and a second delay compensation unit that generates the control signal provided to the first variable delay element included in the second referential delay unit.
The referential delay unit may have a ring oscillator that has different numbers of the first variable delay elements and generates a predetermined period of an oscillation clock according to the numbers of the first variable delay elements.
The delay compensation unit may further have: a phase comparator that compares a phase of a referential clock having a predetermined period with a phase of a delay clock, which is obtained by delaying the referential clock by the first variable delay elements; and a control signal generating unit which generates the control signal based on the comparison.
The control signal generating unit may generate the control signal so that a phase of the referential clock and phase of the delay clock matches.
The variable delay circuit may further comprise a selector that provides any one of a plurality of the control signals provided from the delay compensation unit to the second variable delay elements.
The first variable delay element may have a capacitor that has a predetermined capacitance and a time constant control unit for changing a time constant of the capacitor and may change a delay amount according to the time constant.
The time constant control unit may have a transistor and may change a time constant of the capacitor by changing a gate voltage applied to the transistor.
The second embodiment of the present invention is a variable delay circuit which generates a desired delay amount for a signal to be output to an output terminal that comprises: a variable delay element that has a capacitor having a predetermined capacitance and a time constant control unit, which is serially inserted between the capacitor and the output terminal for changing a time constant of the capacitor, and changes a delay amount according to the time constant; and a delay unit which generates the desired delay amount by selecting the variable delay elements based on the desired delay amount.
The time constant control unit may have a transistor and may change a time constant of the capacitor by changing a gate voltage applied to the transistor.
According to the third embodiment of the present invention, a semiconductor testing apparatus for testing a semiconductor device comprises: a pattern generator for generating a test pattern input to a semiconductor device; a formatted test pattern generator that has: a plurality of referential delay units having different numbers of first variable delay elements, the delay amount of which changes based on a control signal; a delay compensation unit which generates each of a plurality of the control signals provided to the first variable delay elements according to a number of the first variable delay elements; and a delay unit which generates a delay clock having a delay amount according to an operation characteristic of the semiconductor device by controlling a plurality of second variable delay elements having a same characteristic with that of the first variable delay elements by the plurality of control signals; the formatted test pattern generator formats the test pattern based on the delay clock and generates a formatted test pattern; a device contact unit, on which the semiconductor device is installed, for inputting the formatted test pattern to the semiconductor device; and a comparator which judges the quality of the semiconductor device based on an output signal output from the semiconductor device, to which the formatted test pattern is input.
The referential delay unit may have a ring oscillator that has different numbers of the first variable delay element and may generate a predetermined period of an oscillation clock according to the numbers of the first variable delay elements.
The variable delay circuit may further have a selector that provides any one of a plurality of the control signals provided from the delay compensation unit to the second variable delay elements.
The first variable delay element may have a capacitor that has a predetermined capacitance and a time constant control unit for changing a time constant of the capacitor and may change a delay amount according to the time constant.
According to the fourth embodiment of the present invention, a semiconductor device having a semiconductor test unit for testing a semiconductor device comprises: a semiconductor test unit which has: a plurality of referential delay units having different numbers of first variable delay elements, the delay amount of which changes based on a control signal; a delay compensation unit which generates each of a plurality of the control signals provided to the first variable delay elements according to the numbers of the first variable delay elements; a delay unit which generates a timing used for testing a device-under-test unit based on an operation characteristic of the semiconductor device by controlling a plurality of second variable delay elements having a same characteristic with that of the first variable delay elements by the plurality of control signals; and a device-under-test unit to be tested by the semiconductor test unit.
The referential delay unit may have a ring oscillator that has different numbers of the first variable delay elements and generates a predetermined period of an oscillation clock according to the numbers of the first variable delay elements.
The variable delay circuit may further comprise a selector that provides any one of a plurality of the control signals provided from the delay compensation unit to the second variable delay elements.
The first variable delay element may have a capacitor having a predetermined capacitance and a time constant control unit for changing a time constant of the capacitor and may change a delay amount according to the time constant.
According to the fifth embodiment of the present invention, a delay signal generating method for generating a delay signal, which is obtained by delaying an input signal for a desired time, comprises: a step for generating a plurality of clocks by a plurality of referential delay units having different numbers of first variable delay elements, the delay amount of which changes, based on a control signal; a step for comparing each of the phases of a plurality of the clocks and a phase of a referential clock; a step for correcting each of the control signals corresponding to a plurality of the clocks based on the compared phase; a step for controlling each of the delay amounts of the first variable delay elements based on the corrected control signal; and a step for generating the delay signal, which is obtained by delaying the input signal for the desired time by controlling a plurality of second variable delay elements, which receives the control signal and is controlled based on the control signal and has a same characteristic with that of the first variable delay element, based on the corrected control signal.